Defeasible Reasoning via Datalog$^\neg$

Hardware architectures can range from the use of GPUs and other hardware accelerators, through multi-core multi-threaded architectures, to shared-nothing cloud computing. Causes for failure to exploit these architectures include lack of expertise in the architectural features, lack of manpower more generally, and difficulty in updating legacy systems. Such problems can be ameliorated by mapping a logic to logic programming as an intermediate language. This is a common strategy in the implementation of defeasible logics. The first implementation of a defeasible logic, d-Prolog, was implemented as a Prolog meta-interpreter (Covington et al. 1997). Courteous Logic Programs (Grosof 1997) and its successors LPDA (Wan et al. 2009), Rulelog (Grosof and Kifer 2013), Flora2 (Kifer et al. 2018), are implemented in XSB (Swift and Warren 2012).