Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis

They support simple Boolean operations as well as complicated arithmetic operations such as multiplication in a single instruction, multiple data (SIMD) scheme. DSPs have evolved to support a wide range of applications requiring significant amounts of Boolean operations that may not even necessarily fit on the available lookup tables (LUTs) on an FPGA. In addition to the vast computation capabilities, DSP blocks support dynamic runtime programmability, which allows a single DSP block to be used as a different computational block in each clock cycle. Vendor synthesis tools provide capabilities to utilize the available resources on FPGAs; however, existing tool flows such as high-level synthesis tools fail to fully exploit the existing capabilities, especially the dynamic programmability of DSPs. Bajaj et al. [10-14] explore how DSP blocks can be deployed to produce high-throughput computational kernels and how their dynamic programmability can be exploited to create efficient implementations of arithmetic expressions. However, their solution suffers from inefficient mapping when it comes to implementing combinational Boolean functions using DSP blocks.