Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing

RISC-V [1] is rapidly gaining traction as an open, modular, and royalty-free Instruction Set Architecture (ISA). Unlike proprietary ISAs, RISC-V's openness allows researchers and designers to customize the core to application-specific requirements, enabling novel architectural extensions and accelerators. In domains such as wireless communications and edge Machine Learning, one-dimensional (1D) convolutions (and related dot products) are ubiquitous: they underlie Finite Impulse Response (FIR) filters, matched filtering, correlation and synchronization in wireless systems, and convolutional layers in neural networks for time-series data (e.g., audio processing, sensor data analysis). Despite RISC-V's flexibility, a scalar, in-order implementation of the RV32I base ISA (32-bit integer) lacks specialized instructions for the numerous multiply-accumulate (MAC) operations required by convolution. Software implementations on such a core execute a sequence of load, multiply, add, and store instructions for each convolution tap, resulting in high cycle counts and energy consumption-especially problematic in real-time, battery-powered edge deployments.