Row-Column Hybrid Grouping for Fault-Resilient Multi-Bit Weight Representation on IMC Arrays

--This paper addresses two critical challenges in analog In-Memory Computing (IMC) systems that limit their scalability and deployability: the computational unreliability caused by stuck-at faults (SAFs) and the high compilation overhead of existing fault-mitigation algorithms, namely Fault-Free (FF). T o overcome these limitations, we first propose a novel multi-bit weight representation technique, termed row-column hybrid grouping, which generalizes conventional column grouping by introducing redundancy across both rows and columns. This structural redundancy enhances fault tolerance and can be effectively combined with existing fault-mitigation solutions. Further acceleration is achieved through theoretical insights that identify fault patterns amenable to trivial solutions, significantly reducing computation. Experimental results on convolutional networks and small language models demonstrate the effectiveness of our approach, achieving up to 8%p improvement in accuracy, 150 faster compilation, and 2 energy efficiency gain compared to existing baselines. The In-Memory Computing (IMC) paradigm marks a trans-formative shift toward non-von Neumann architectures by allowing data processing to occur directly within the memory array [1]-[4], thereby minimizing the overhead associated with off-chip data movement [5]. Among various implementations, analog IMC systems based on Resistive Random Access Memory (ReRAM) crossbar arrays have emerged as a particularly promising solution. These systems perform energy-efficient matrix-vector multiplication (MVM) [3], [4], a core operation that forms the computational backbone of modern deep learning systems. As such, analog IMC has become a focal point in DNN acceleration and efficient AI research, spearheading cutting-edge investigations in approximate computing, heterogeneous computing, and alternative learning paradigms. To perform MVM in the analog domain, the weights are stored as conductance values in ReRAM cells; input features are applied as voltages to the word lines, and the resulting bit-line currents naturally multiply-and-accumulate following Ohm's and Kirchhoff's laws [6], [7].