GATMesh: Clock Mesh Timing Analysis using Graph Neural Networks

--Clock meshes are essential in high-performance VLSI systems for minimizing skew and handling PVT variations, but analyzing them is difficult due to reconvergent paths, multi-source driving, and input mesh buffer skew. SPICE simulations are accurate but slow; yet simplified models miss key effects like slew and input skew. We propose GA TMesh, a Graph Neural Network (GNN)-based framework that models the clock mesh as a graph with augmented structural and physical features. Trained on SPICE data, GA TMesh achieves high accuracy with average delay error of 5.27ps on unseen benchmarks, while achieving speed-ups of 47146x over multi-threaded SPICE simulation. Clock distribution networks (CDNs) are fundamental to high-performance VLSI designs, ensuring precise synchronization across millions of sequential elements. Among various architectures, clock meshes stand out for their superior robustness against process, voltage, and temperature (PVT) variations, offering low clock skew and improved tolerance to uncertainties in modern fabrication processes. By leveraging multiple redundant paths as shown in Figure 1, clock meshes effectively distribute the clock signal across the chip. However, these advantages come with significant challenges. One of the primary difficulties in analyzing clock meshes arises from the simultaneous multi-source driving of the network. These sources originate from an underlying clock tree, where variations in delay among different branches introduce varying input arrival times to the mesh.