AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs

--Recently, the use of large language models (LLMs) for software code generation, e.g., C/C++ and Python, has proven a great success. However, LLMs still suffer from low syntactic and functional correctness when it comes to the generation of register-transfer level (RTL) code, such as V erilog. T o address this issue, in this paper, we develop AutoVCoder, a systematic open-source framework that significantly improves the LLMs' correctness of generating V erilog code and enhances the quality of its output at the same time. Experimental results demonstrate that AutoVCoder outperforms both industrial and academic LLMs in V erilog code generation. Specifically, AutoVCoder shows a 0.5% and 2.2% improvement in functional correctness on the EvalMachine and EvalHuman benchmarks compared with BetterV, and also achieves a 3.4% increase in syntax correctness and a 3.4% increase in functional correctness on the RTLLM benchmark compared with RTLCoder . I. I NTRODUCTION Large Language Models (LLMs) has increasingly captured the attention of the academia and industry. In the realm of programming, LLMs have demonstrated remarkable success in generating software code, automating and streamlining the development process of programming languages like C, C++, and Python. Recently, some representative works [1, 2, 3, 4, 5, 6], including CodeT5 [1], CodeGen [2], CodeGeeX [3], have made tremendous breakthroughs in augmenting LLMs for software code generation. Additionally, commercial tools such as Copilot [7] and GPT -4 [8] have demonstrated notable performance in code generation. The progress is largely driven by advances in model architecture, training techniques, and most importantly, the vast amounts of data on which these models are trained.