DPUV4E: High-Throughput DPU Architecture Design for CNN on Versal ACAP

--Convolutional Neural Networks (CNNs) remain prevalent in computer vision applications, and FPGAs, known for their flexibility and energy efficiency, have become essential components in heterogeneous acceleration systems. AMD's V ersal ACAP architecture, tailored for AI applications, incorporates AI Engines (AIEs) to deliver high computational power . Nevertheless, the platform suffers from insufficient memory bandwidth, hindering the full utilization of the AIEs' theoretical performance. We design two computation units, Conv PE and DWC PE, to support different computational patterns. Each computation unit's data flow efficiently utilizes the data reuse opportunities to mitigate bandwidth bottlenecks. Additionally, we extend the functionality of each PE to utilize AIEs for non-convolutional operations, reducing resource overhead. Experiments on over 50 models show that compared to previous designs, our design provides 8 . At present, deep learning (DL) has profoundly integrated into our daily lives. Despite the emergence of new transformer-based neural networks, Convolutional Neural Networks (CNN) remain extensively employed owing to their proficiency in extracting local information from images in relatively smaller datasets. GPUs' efficient parallel processing is used to improve CNN inference, but their general-purpose design reduces energy efficiency. To improve accelerators' energy efficiency and throughput, custom CNN architectures have been proposed.