HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL

Recent advances in large language models (LLMs) have demonstrated remarkable capabilities in code generation tasks. However, when applied to hardware description languages (HDL), these models exhibit significant limitations due to data scarcity, resulting in hallucinations and incorrect code generation. To address these challenges, we propose HDLCoRe, a training-free framework that enhances LLMs' HDL generation capabilities through prompt engineering techniques and retrieval-augmented generation (RAG). Our approach consists of two main components: (1) an HDL-aware Chain-of-Thought (CoT) prompting technique with self-verification that classifies tasks by complexity and type, incorporates domainspecific knowledge, and guides LLMs through step-by-step self-simulation for error correction; and (2) a two-stage heterogeneous RAG system that addresses formatting inconsistencies through key component extraction and efficiently retrieves relevant HDL examples through sequential filtering and re-ranking. HDLCoRe eliminates the need for model fine-tuning while substantially improving LLMs' HDL generation capabilities. Experimental results demonstrate that our framework achieves superior performance on the RTLLM2.0 With the rapid advancement of semiconductor technology, the design of very large-scale integration (VLSI) has become increasingly vital across industries Huang et al. (2021). Hardware description language (HDL) code, as the foundation of VLSI design, plays a critical role in defining the circuit architecture and functionality Palnitkar (2003). In recent years, large language models (LLMs) have experienced explosive growth and demonstrated extraordinary capabilities in many aspects Kanakaris et al. (2025); Li et al. (2025), especially in automated code generation Brown et al. (2020); Chen et al. (2021).