A CMOS Probabilistic Computing Chip With In-situ hardware Aware Learning

University of California Santa Barbara, Santa Barbara, USA Abstract This paper demonstrates a probabilistic bit physics - inspired solver with 440 spins configured in a Chimera graph and occupying an area of 0. 44 mm . Area efficiency was maximized through a current - mode implementation of neuron update circuit, standard cell design for analog blocks pitch - matched to digital block, and a shared power supply for digital and analog components. Process variation related m ismatches introduced by this approach were effectively mitigated using a hardware - aware contrastive divergence algorithm during training. We validate the chip's ability to perform probabilistic computing tasks, such as modeling logic gates and full adde rs and optimization tasks, such as Max - Cut. demonstrate its potential for AI and machine learning. Keywords (optional): Ising, p - bit, hardware - aware learning Introduction Probabilistic bits (p - bits) have emerged as a hardware friendly approach for solving optimization problems, machine learning, quantum inspired computing and AI [1].