Bayesian Inference on Binary Spiking Networks Leveraging Nanoscale Device Stochasticity

Abstract--Bayesian Neural Networks (BNNs) can overcome the problem of overconfidence that plagues traditional frequentist deep neural networks, and are hence considered to be a key enabler for reliable AI systems. In this paper, we introduce a novel Phase Change Memory (PCM)-based hardware implementation for BNNs with binary synapses. The proposed architecture consists of separate weight and noise planes, in which PCM cells are configured (b) Proposed hardware architecture consisting of a N M crossbar and operated to represent the nominal values of weights and of differential PCM (DPCM) cells, referred to as the weight to generate the required noise for sampling, respectively. We choose L < M and reuse hardware accuracy and expected calibration error matching that the conductance values from the L rows in the noise plane stored of an 8-bit fixed-point (FxP8) implementation, with projected in a register through stochastic arbitration (SA), in order to reduce savings of over 9 in terms of core area transistor count. Non-volatile memory (NVM) devices such as Resistive RAM (RRAM), Phase Change Memory (PCM) and Spin-Modern neural networks tend to produce overconfident decisions, Transfer Torque RAM (STTRAM) are being explored for misrepresenting the inherent epistemic uncertainty that the implementation of in-memory computing (IMC) architectures arises from access to limited data [1].