NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities

--The exponential growth of artificial intelligence (AI) applications has exposed the inefficiency of conventional von Neumann architectures, where frequent data transfers between compute units and memory create significant energy and latency bottlenecks. However, designing robust ACIM accelerators requires accurate modeling of device-and circuit-level non-idealities. In this work, we present NeuroSim V1.5, introducing several key advances: (1) seamless integration with T ensorRT's post-training quantization flow enabling support for more neural networks including transformers, (2) a flexible noise injection methodology built on pre-characterized statistical models, making it straightforward to incorporate data from SPICE simulations or silicon measurements, (3) expanded device support including emerging non-volatile capacitive memories, and (4) up to 6.5 faster runtime than NeuroSim V1.4 through optimized behavioral simulation. The combination of these capabilities uniquely enables systematic design space exploration across both accuracy and hardware efficiency metrics. Through multiple case studies, we demonstrate optimization of critical design parameters while maintaining network accuracy. HE exponential growth in AI applications has exposed a critical challenge in energy-efficient computing. The fundamental limitation lies in the mismatch between the memory-centric workloads such as in machine learning algorithms and the processing-centric architecture in contemporary hardware platforms. This mismatch causes massive data movement between memory and processing units to consume more than five times the energy of computation [1]. This work is supported in part by PRISM, one of the SRC/DARP A JUMP 2.0 Centers. J. Read acknowledges support from the DoD's SCALE program. The authors are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, 30332 USA (email: jread6@gatech.edu) Compute-in-memory (CIM) has emerged as a promising paradigm to tackle this bottleneck by co-locating data storage and multiply-accumulate (MAC) operations in the same physical arrays, thereby reducing repeated weight fetches. In digital computing-in-memory (DCIM), memory arrays (typically made of modified SRAM bit cells) are augmented with digital multipliers and adder trees for partial-sum accumulation, delivering robust performance with the overhead of adder trees [3].