Towards Programmable Memory Controller for Tensor Decomposition

Field Programmable Gate Arrays (FPGAs) are an attractive platform to accelerate CPD due to the vast Recent advances in collecting and analyzing large inherent parallelism and energy efficiency FPGAs can datasets have led to the information being naturally offer. Since sparse MTTKRP is memory bound, improving represented as higher-order tensors. Tensor Decomposition the sustained memory bandwidth and latency transforms input tensors to a reduced latent between the compute units on the FPGA and the external space which can then be leveraged to learn salient features DRAM memory can significantly reduce the of the underlying data distribution. Tensor Decomposition MTTKRP compute time. FPGA facilitates near memory has been successfully employed in many computing with custom adaptive hardware due fields, including machine learning, signal processing, to its reconfigurability and large on-chip BlockRAM and network analysis (Mondelli and Montanari, 2019; memory (Xilinx, 2019). It enables the development Cheng et al., 2020; Wen et al., 2020). Canonical of memory controllers and compute units specialized Polyadic Decomposition (CPD) is the most popular for specific data formats; such customization is not means of decomposing a tensor to a low-rank tensor supported on CPU and GPU.