Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs

-- We introduce a mapping framework for deep learning inference that takes advantage of predictable neural network behavior to plan both computation and communication ahead of time. The framework generates a unified stream of instructions and data, enabling t he hardware to execute operations and route information on its own, without frequent involvement from the host and with minimal off - chip memory use. This naturally reduces reliance on I/O, off - chip memory, and host control. By leveraging fine - grained messa ge passing on a programmable, message - based compute architecture, the framework keeps data movement local and coordinates computation across the array using techniques such as stationary - weight reuse, in - array multicasting, and staged reductions. Applied t o VGG - 19, the framework sustains high utilization (88 to 92 percent), with over 97 percent of messages generated internally and nearly 89 percent of time consumed on - chip transfers. Overall, the results highlight the effectiveness of streaming - based computation and show how our mapper enables this execution style by tightly coordinating data and instruction flow across the hardware. Transitioning across layers or handling boundaries (e.g., padding or strides) requires flushing state and reprogramming the array, which breaks opportunities for reuse In our work, we take the view that deep - learning inference is structured enough to shift control away from the host.