NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic

QAT refers to the quantization of activations to binary, bipolar, or multi-bit values during neural network training. On the other hand, if deep neural networks (DNNs) [1]-[31], ultra-low-latency realization a set of values can only assume non-negative numbers, it relies on of these models for applications with stringent, sub-microsecond the parameterized clipping activation (PACT) [9] function to quantize latency requirements continues to be an unresolved, challenging activations. Field-programmable gate array (FPGA)-based DNN accelerators FCP applies fanin constraints to individual filters/neurons such that are gaining traction as a serious contender to replace graphics the number of inputs to each filter/neuron is small enough to make processing unit/central processing unit-based platforms considering a realization based on input enumeration (as described in NullaNet their performance, flexibility, and energy efficiency. In this work, FCP is either based on the alternating [32], LUTNet (2019) [33], and LogicNets (2020) [34] are among accelerators direction method of multipliers [35] or gradual pruning [11]. Finally, functions of different filters/neurons are represented using This paper presents NullaNet Tiny, an across-the-stack design truth tables which are then fed to the logic minimization module.