Can LLMs Revolutionize the Design of Explainable and Efficient TinyML Models?

--This paper introduces a novel framework for designing efficient neural network architectures specifically tailored to tiny machine learning (TinyML) platforms. The LLM-guided search explores a hierarchical search space, refining candidate architectures through Pareto optimization based on accuracy, multiply-accumulate operations (MACs), and memory metrics. The best-performing architectures are further fine-tuned using logits-based KD with a pre-trained ViT-B/16 model, which enhances generalization without increasing model size. Evaluated on the CIF AR-100 dataset and deployed on an STM32H7 microcontroller (MCU), the three proposed models, LMaNet-Elite, LMaNet-Core, and QwNet-Core, achieve accuracy scores of 74.50%, 74.20% and 73.00%, respectively. All three models surpass current state-of-the-art (SOT A) models, such as MCUNet-in3/in4 (69.62% / 72.86%) and XiNet (72.27%), while maintaining a low computational cost of less than 100 million MACs and adhering to the stringent 320 KB static random-access memory (SRAM) constraint. These results demonstrate the efficiency and performance of the proposed framework for TinyML platforms, underscoring the potential of combining LLM-driven search, Pareto optimization, KD, and explainability to develop accurate, efficient, and interpretable models. This approach opens new possibilities in NAS, enabling the design of efficient architectures specifically suited for TinyML. T o facilitate further research and development in this field, the proposed framework and the best-performing architectures are made publicly available at Link. The proliferation of internet of things (IoT) devices built on tiny hardware platforms, such as microcontrollers (MCUs), has underscored the demand for deploying deep learning (DL) models in resource-constrained environments [1]. Despite their potential to democratize artificial intelligence (AI), these devices face unique challenges that differ significantly from mobile DL, particularly due to stringent memory limitations. For instance, the typical MCU has a static random-access memory (SRAM) of less than 512kB, which poses a substantial obstacle for running conventional DL models [2]. Numerous lightweight deep neural network (DNN) architectures, such as MobileNet [3], have demonstrated the utility of handcrafted model design for mobile applications. Y et, when adapted for MCUs, the limited memory resources pose significant hurdles. Our proposed architectures balance accuracy and efficiency, reducing model size and computational cost compared to baselines.