Unsupervised Graph Neural Network Framework for Balanced Multipatterning in Advanced Electronic Design Automation Layouts

Abstract-- Multipatterning is an essential decomposition strategy in electronic design automation (EDA) that overcomes lithographic limitations when printing dense circuit layouts. Although heuristic-based backtracking and SA T solvers can address these challenges, they often struggle to simultaneously handle both complex constraints and secondary objectives. In this study, we present a hybrid workflow that casts multipatterning as a variant of a constrained graph coloring problem with the primary objective of minimizing feature violations and a secondary objective of balancing the number of features on each mask. Our pipeline integrates two main components: (1) A GNN-based agent, trained in an unsupervised manner to generate initial color predictions, which are refined by (2) refinement strategies (a GNN-based heuristic and simulated annealing) that together enhance solution quality and balance. Experimental evaluation in both proprietary data sets and publicly available open source layouts demonstrate complete conflict-free decomposition and consistent color balancing. The proposed framework provides a reproducible, data-efficient and deployable baseline for scalable layout decomposition in EDA workflows. As semiconductor technology progresses, the demand for higher circuit densities continues to surpass the limits of conventional lithographic techniques. The ongoing reduction in feature size introduces increasingly complex manufacturing constraints, making it difficult to accurately print intricate patterns on a single mask without defects. To address these challenges, modern electronic design automation (EDA) tools and fabrication processes rely on multipatterning, which is a layout decomposition technique that ensures manufacturability while preserving design integrity. In modern integrated circuit (IC) design, Design Rule Checking (DRC) is a critical step that ensures that the physical layout complies with a set of rules derived from the manufacturing constraints. These rules include the requirements on spacing, width, enclosure, and other geometric and connectivity constraints.