They power our phones, cars, dishwashers--and the A.I. systems that prop up the economy. "We don't have a rating scale for complexity, but rockets are maybe a five," an investor said. His partner added, "Semiconductors are an eleven." There are a handful of truly monumental collective achievements in our history: Machu Picchu, the Great Wall of China, the Pyramids of Giza, and perhaps, if we're being generous, the Roman aqueducts. Modern global civilization has made one contribution to this eternal pantheon. It is not the moon landing. It is the semiconductor supply chain. A microchip is a bauble of metal and refined sand. It doesn't appear to have epic proportions. Upon close examination, however, the epic proportions are there in miniature. Imagine a perfect replica of a sprawling metropolis, a Tokyo or a São Paulo, engraved at atomic dimensions on a tile the size of a fingernail. The urban details would be faithfully rendered to the last golf ball or egg--each reduced to ...

How far can we push computing? Nowadays big advances are made by scaling up--think more chips packed into ever-bigger data centers. But as we near the ceiling of what we can build, there's still plenty of room below, at the fundamental physical limits of computing. Richard Feynman speaks at CERN in Geneva, Switzerland, in 1965. On the evening of December 29, 1959, at an American Physical Society meeting at Caltech, the physicist Richard Feynman gave a lecture called "There's Plenty of Room at the Bottom," on how we might manipulate and control things on an extremely small scale. There is no physical law stopping us from writing the entire on the head of a pin, he argued, or from storing every book ever written in something the size of a dust speck--or, ultimately, from arranging matter atom by atom. Biology already did versions of this (a living cell keeps its instructions in a wisp of DNA), so all of this was plainly permitted by the laws of physics. We simply had not built the tools yet.

How a tiny little electronic switch sparked the computer revolution. Last week I revealed the sneaky physics behind the " joule thief," an electrical circuit that lets you squeeze more energy out of seemingly dead batteries. The key, it turned out, was a clever pairing of a transformer and a transistor. But the transistor deserves its own headline, because it's maybe only the most important invention of the 20th century. Life would be completely different without transistors.

IBM hails new'block of flats' design breakthrough for ultra tiny chips Image caption, IBM's new sub-1 nm chip crams almost 100 billion transistors onto a surface the size of a fingernail IBM has unveiled a new chip design which it says could enable manufacturers to cram 100 billion transistors on a silicon chip the size of a fingernail. The current industry-standard size for chips, measured in a the unit of nanometres - a billionth of a metre and the size of a few atoms - is around two nanometres (nm). But IBM claims its new chip tech is the equivalent of around 0.7nm, which may make it the world's first known chip technology below 1nm. However, it will be several years before the chip tech could be ready to go into production. The firm claims in tests, its prototype performed 50% better than its own 2nm chip and was 70% more energy efficient.

Large Language Models (LLMs) and transformer architectures have shown impressive reasoning and generation capabilities across diverse natural language tasks. However, their reliability and robustness in real-world engineering domains remain largely unexplored, limiting their practical utility in human-centric workflows. In this work, we investigate the applicability and consistency of LLMs for analog circuit design -- a task requiring domain-specific reasoning, adherence to physical constraints, and structured representations -- focusing on AI-assisted design where humans remain in the loop. We study how different data representations influence model behavior and compare smaller models (e.g., T5, GPT-2) with larger foundation models (e.g., Mistral-7B, GPT-oss-20B) under varying training conditions. Our results highlight key reliability challenges, including sensitivity to data format, instability in generated designs, and limited generalization to unseen circuit configurations. These findings provide early evidence on the limits and potential of LLMs as tools to enhance human capabilities in complex engineering tasks, offering insights into designing reliable, deployable foundation models for structured, real-world applications.

The growing demand for low-power and area-efficient TinyML inference on AIoT devices necessitates memory architectures that minimise data movement while sustaining high computational efficiency. This paper presents FERMI-ML, a Flexible and Resource-Efficient Memory-In-Situ (MIS) SRAM macro designed for TinyML acceleration. The proposed 9T XNOR-based RX9T bit-cell integrates a 5T storage cell with a 4T XNOR compute unit, enabling variable-precision MAC and CAM operations within the same array. A 22-transistor (C22T) compressor-tree-based accumulator facilitates logarithmic 1-64-bit MAC computation with reduced delay and power compared to conventional adder trees. The 4 KB macro achieves dual functionality for in-situ computation and CAM-based lookup operations, supporting Posit-4 or FP-4 precision. Post-layout results at 65 nm show operation at 350 MHz with 0.9 V, delivering a throughput of 1.93 TOPS and an energy efficiency of 364 TOPS/W, while maintaining a Quality-of-Result (QoR) above 97.5% with InceptionV4 and ResNet-18. FERMI-ML thus demonstrates a compact, reconfigurable, and energy-aware digital Memory-In-Situ macro capable of supporting mixed-precision TinyML workloads.

Utilizing the intrinsic history-dependence and nonlinearity of hardware, physical reservoir computing is a promising neuromorphic approach to encode time-series data for in-sensor computing. The accuracy of this encoding critically depends on the distinguishability of multi-state outputs, which is often limited by suboptimal and empirically chosen reservoir operation conditions. In this work, we demonstrate a machine learning approach, Bayesian optimization, to improve the encoding fidelity of solution-processed Al2O3/In2O3 thin-film transistors (TFTs). We show high-fidelity 6-bit temporal encoding by exploring five key pulse parameters and using the normalized degree of separation (nDoS) as the metric of output state separability. Additionally, we show that a model trained on simpler 4-bit data can effectively guide optimization of more complex 6-bit encoding tasks, reducing experimental cost. Specifically, for the encoding and reconstruction of binary-patterned images of a moving car across 6 sequential frames, we demonstrate that the encoding is more accurate when operating the TFT using optimized pulse parameters and the 4-bit optimized operating condition performs almost as well as the 6-bit optimized condition. Finally, interpretability analysis via Shapley Additive Explanations (SHAP) reveals that gate pulse amplitude and drain voltage are the most influential parameters in achieving higher state separation. This work presents the first systematic method to identify optimal operating conditions for reservoir devices, and the approach can be extended to other physical reservoir implementations across different material platforms.

Next to the flashy realm of AI, materials may seem quaint. These days, our lives revolve around the digital world. Money, culture, news, gossip - all of it lives there. Generative artificial intelligence is the biggest story in the world, but could you point to where that technology is physically located? The material world just isn't where the action is.

The humble inventions that power our modern world wouldn't have been possible without decades of support for early-stage research. In December 1947, three physicists at Bell Telephone Laboratories--John Bardeen, William Shockley, and Walter Brattain--built a compact electronic device using thin gold wires and a piece of germanium, a material known as a semiconductor. Their invention, later named the transistor (for which they were awarded the Nobel Prize in 1956), could amplify and switch electrical signals, marking a dramatic departure from the bulky and fragile vacuum tubes that had powered electronics until then. They were asking fundamental questions about how electrons behave in semiconductors, experimenting with surface states and electron mobility in germanium crystals. Over months of trial and refinement, they combined theoretical insights from quantum mechanics with hands-on experimentation in solid-state physics--work many might have dismissed as too basic, academic, or unprofitable. Their efforts culminated in a moment that now marks the dawn of the information age.

The design of Analog and Mixed-Signal (AMS) integrated circuits (ICs) often involves significant manual effort, especially during the transistor sizing process. While Machine Learning techniques in Electronic Design Automation (EDA) have shown promise in reducing complexity and minimizing human intervention, they still face challenges such as numerous iterations and a lack of knowledge about AMS circuit design. Recently, Large Language Models (LLMs) have demonstrated significant potential across various fields, showing a certain level of knowledge in circuit design and indicating their potential to automate the transistor sizing process. In this work, we propose an LLM-based AI agent for AMS circuit design to assist in the sizing process. By integrating LLMs with external circuit simulation tools and data analysis functions and employing prompt engineering strategies, the agent successfully optimized multiple circuits to achieve target performance metrics. We evaluated the performance of different LLMs to assess their applicability and optimization effectiveness across seven basic circuits, and selected the best-performing model Claude 3.5 Sonnet for further exploration on an operational amplifier, with complementary input stage and class AB output stage. This circuit was evaluated against nine performance metrics, and we conducted experiments under three distinct performance requirement groups. A success rate of up to 60% was achieved for reaching the target requirements. Overall, this work demonstrates the potential of LLMs to improve AMS circuit design.