Google Details New TensorFlow Optimized ASIC

Norm Jouppi, a distinguished hardware engineer at Google, detailed the company's public disclosure of the Tensor Processing Unit (TPU) last week after the CEO Sundar Pichai's earlier announcement at Google I/O. ASIC optimizations, reportedly favoring machine learning with TensorFlow (TF) specifically, include reduced computational precision, thereby requiring fewer transistors per operation. Performance-testing parameters or metrics aren't available at this time, but Google claimed the optimizations help increase the number of operations per second the chip can process. Google noted that the project was started several years ago and that it was fast-forwarding current technology by about seven years but hasn't provided data for the community to analyze. Jouppi noted the time from testing a prototype of the chip to data-center deployment was 22 days and that it was an example of Google putting research into practice.