Semiconductor Engineering .:. Overcoming The Limits Of Scaling

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with Sundari Mitra, CEO of NetSpeed Systems; Charlie Janac, chairman and CEO of Arteris; Simon Davidmann CEO of Imperas; John Koeter, vice president of marketing for IP and prototyping at Synopsys; and Chris Rowen, a consultant at Cadence. What follows are excerpts of that conversation. SE: Can IP be designed for an entire system, and does that change what has to be done architecturally? Janac: If you are using layers and stacks, you can go all the way from layout into architecture for a particular piece of a chip. It gets used by the architect, by the RTL developer, by the layout person, by the verification engineer, for what is essentially a vertical slice of the chip.