Digital-Analog Hybrid Synapse Chips for Electronic Neural Networks

Electronic synapses based on CMOS, EEPROM, as well as thin film technologies are actively being developed [1-5]. One preferred approach is based on a hybrid digital-analog design which can easily be implemented in CMOS with simple interface and analog circuitry. The hybrid design utilizes digital memories to store the synaptic weights and digital-to-analog converters to perform analog multiplication. A variety of synaptiC chips based on such hybrid designs have been developed and used as "building blocks" in larger neural network hardware systems fabricated at JPL. In this paper, the design and operational characteristics of the hybrid synapse chips are described.