A Bit-Parallel Deterministic Stochastic Multiplier

Abstract--This paper presents a novel bit-parallel deterministic stochastic multiplier, which improves the area-energy-latency product by up to 10.6 10 In SC's unipolar format, W is an SB of N bits GEMM circuits used in deep learning accelerators [2]. Stochastic multipliers suffer from computational errors. Our proposed reduced lengths and deterministic bit-position correlations in multiplier achieves 32.2%, 42.8%, and 51.8% lower MAE a bit-parallel manner, thereby simultaneously minimizing the compared to uMUL [2], Jenson [3], and Gaines [1], respectively. In addition, our proposed multiplier achieves 10.6 10 Our multiplier achieves that as follows.