Recursive Learning-Based Virtual Buffering for Analytical Global Placement

--With scaling of interconnect versus gate delays in advanced technology nodes, placement with buffer porosity awareness is essential for timing closure in physical synthesis flows. However, existing approaches face two key challenges: (i) traditional van Ginneken-Lillis-style buffering approaches [20], [27] are computationally expensive during global placement; and (ii) machine learning-based approaches, such as BufFormer [18], omit important Electrical Rule Check (ERC) considerations and typically fail to "close the loop" back into the physical design flow. In this work, we propose MLBuf-RePlAce, an open-source learning-driven virtual buffering-aware analytical global placement framework, built on top of the OpenROAD infrastructure [34]. MLBuf-RePlAce adopts an efficient recursive learning-based generative buffering approach to predict buffer types and locations, addressing ERC violations during global placement. We compare MLBuf-RePlAce against the default virtual buffering-based timing-driven global placer in OpenROAD, using open-source testcases from the TILOS MacroPlacement [36] and OpenROAD-flow-scripts [33] repositories. Without degradation of post-route power, MLBuf-RePlAce achieves (maximum, average) improvements of (56%, 31%) in total negative slack (TNS) within the open-source OpenROAD flow. When evaluated by completion in a commercial flow, MLBuf-RePlAce achieves (maximum, average) improvements of (53%, 28%) in TNS with an average of 0.2% improvement in post-route power . Global placement is a critical step in VLSI physical design. State-of-the-art analytical global placers [8] [11] [14] [22] typically adopt the electrostatics-based placement approach [23], formulating global placement as nonlinear programming under density constraints. Additionally, for design implementation in advanced technology nodes, timing closure requires extensive buffer insertion [18] and brings a complex interplay with global placement.