HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions

--High-level synthesis (HLS) accelerates hardware design by enabling the automatic translation of high-level descriptions into efficient hardware implementations. However, debugging HLS code is a challenging and labor-intensive task, especially for novice circuit designers or software engineers without sufficient hardware domain knowledge. The recent emergence of Large Language Models (LLMs) is promising in automating the HLS debugging process. Despite the great potential, three key challenges persist when applying LLMs to HLS logic debugging: 1) High-quality circuit data for training LLMs is scarce, posing a significant challenge. HLSDebugger first generates and releases a large labeled dataset with 300K data samples, targeting HLS logic bugs. The HLSDebugger model adopts an encoder-decoder structure, performing bug location identification, bug type prediction, and bug correction with the same model. HLSDebugger significantly outperforms advanced LLMs like GPT -4 in bug identification and by more than 3 in bug correction. It makes a substantial advancement in the exploration of automated debugging of HLS code. High-Level Synthesis (HLS) has revolutionized the hardware design process by allowing designers to define hardware functionality using high-level programming languages, such as C++ or SystemC. Such a high-level abstraction of circuits accelerates the design process and thus enables rapid prototyping and agile development of hardware.