FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design

--AI hardware design is advancing rapidly, driven by the promise of design automation to make chip development faster, more efficient, and more accessible to a wide range of users. However, their potential is hindered by data privacy concerns and the lack of domain-specific training. T o address this, we introduce FedChip, a Fed erated fine-tuning approach that enables multiple Chip design parties to collaboratively enhance a shared LLM dedicated for automated hardware design generation while protecting proprietary data. FedChip enables parties to train the model on proprietary local data and improve the shared LLM's performance. T o exemplify FedChip's deployment, we create and release APTPU-Gen, a dataset of 30k design variations spanning various performance metric values such as power, performance, and area (PPA). T o encourage the LLM to generate designs that achieve a balance across multiple quality metrics, we propose a new design evaluation metric, Chip@k, which statistically evaluates the quality of generated designs against predefined acceptance criteria. Experimental results show that FedChip improves design quality by more than 77% over high-end LLMs while maintaining data privacy. The global Artificial Intelligence (AI) hardware market, fueled by innovations in deep learning accelerators, autonomous systems, and data-intensive applications, is expected to be worth $84.9 billion by 2031 [1].