Estimating Voltage Drop: Models, Features and Data Representation Towards a Neural Surrogate

Abstract--Accurate estimation of voltage drop (IR drop) in modern Application-Specific Integrated Circuits (ASICs) is highly time and resource demanding, due to the growing complexity and the transistor density in recent technology nodes. To mitigate this challenge, we investigate how Machine Learning (ML) techniques, including Extreme Gradient Boosting (XGBoost), Convolutional Neural Network (CNN), and Graph Neural Network (GNN) can aid in reducing the computational effort and implicitly the time required to estimate the IR drop in Integrated Circuits (ICs). ML algorithms, on the other hand, are explored as an alternative solution to offer quick and precise IR drop estimation, but in considerably less time. This study illustrates the effectiveness of ML algorithms in precisely estimating IR drop and optimizing ASIC sign-off. Thus, a new round of simulations is required for verification. This process is a standard routine in every ASIC design and manufacturing process, and it is defined as the "sign-off" REDICTION of IR drop is an important problem faced today often by ASIC designers. As the current (I) flows With the transition to larger density integration of transistors, through the Power Distribution Network (PDN), a part of the number of connection layers and interconnections the applied voltage inherently drops across the current path, have increased exponentially over the last decades, driven which is, in simple terms, the definition of IR drop. As a result, while commercial results in voltage drop, or to the grounding (GND), which tools are trying to keep up with the up-scaling demand, results in a ground bounce.