Timing-Driven Global Placement by Efficient Critical Path Extraction

Initially, vanilla DREAMPlace [20] is run to distribute the cells within the layout. Subsequently, we perform a path-level timing analysis every m rounds to extract critical paths and update the pin-to-pin loss. This involves report_timing_endpoint(n,1), where n denotes the number of all failing endpoints, to collect data on critical paths. As we traverse these paths, each pin pair (i, j) involved is added to a maintained set P, unless it has already been included. To address the path-sharing effect, the weight w ( i,j) of each pin pair is dynamically updated as follows: w ( i,j) = null w 0, if ( i, j) / P, w (i,j) + w 1 (slack/ WNS), otherwise, (9) where w 0 and w 1 are hyperparameters, and slack indicates the negative slack of the respective critical path. The pin-to-pin attraction loss PP (x, y) of the layout is then computed as: PP (x, y) = null (i,j) P w ( i,j) Q(i, j), (10) with Q(i, j) and w (i,j) defined in Eqs. 8 and 9, respectively. After defining the loss function properly, we implement the CUDA kernel of PP loss for GPU-acceleration.