Nowadays integrated circuits (ICs) are underpinning all major information technology innovations including the current trends of artificial intelligence (AI). Modern IC designs often involve analyses of complex phenomena (such as timing, noise, and power etc.) for tens of billions of electronic components, like resistance (R), capacitance (C), transistors and gates, interconnected in various complex structures. Those analyses often need to strike a balance between accuracy and speed as those analyses need to be carried out many times throughout the entire IC design cycles. With the advancement of AI, researchers also start to explore news ways in leveraging AI to improve those analyses. This paper focuses on one of the most important analyses, timing analysis for interconnects. Since IC interconnects can be represented as an RC-tree, a specialized graph as tree, we design a novel tree-based graph neural network, SyncTREE, to speed up the timing analysis by incorporating both the structural and physical properties of electronic circuits. Our major innovations include (1) a two-pass message-passing (bottom-up and top-down) for graph embedding, (2) a tree contrastive loss to guide learning, and (3) a closed formular-based approach to conduct fast timing. Our experiments show that, compared to conventional GNN models, SyncTREE achieves the best timing prediction in terms of both delays and slews, all in reference to the industry golden numerical analyses results on real IC design data.

Generative AI tools have become more prevalent in engineering workflows, particularly through chatbots and code assistants. As the perceived accuracy of these tools improves, questions arise about whether and how those who work in high-precision domains might maintain vigilance for errors, and what other aspects of using such tools might trouble their work. This paper analyzes interviews with hardware and software engineers, and their collaborators, who work in integrated circuit design to identify the role accuracy plays in their use of generative AI tools and what other forms of trouble they face in using such tools. The paper inventories these forms of trouble, which are then mapped to elements of generative AI systems, to conclude that controlling the context of interactions between engineers and the generative AI tools is one of the largest challenges they face. The paper concludes with recommendations for mitigating this form of trouble by increasing the ability to control context interactively.

Nowadays integrated circuits (ICs) are underpinning all major information technology innovations including the current trends of artificial intelligence (AI). Modern IC designs often involve analyses of complex phenomena (such as timing, noise, and power etc.) for tens of billions of electronic components, like resistance (R), capacitance (C), transistors and gates, interconnected in various complex structures. Those analyses often need to strike a balance between accuracy and speed as those analyses need to be carried out many times throughout the entire IC design cycles. With the advancement of AI, researchers also start to explore news ways in leveraging AI to improve those analyses. This paper focuses on one of the most important analyses, timing analysis for interconnects.

The new model was recently added to NVIDIA’s marquee Omniverse platform.. “NVIDIA’s Get3D is a Generative AI Model for 3D Shapes” is published by Jesus Rodriguez.

SAN DIEGO, Nov. 16, 2021 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCHD) ("GBT" or the "Company"), is developing machine learning based software solutions to include integrated circuit design, verification and manufacturing aspects under one platform, enabling faster design, higher performance, and silicon yield. Based on its recent patented technology, GBT has started the development of a comprehensive software solution to address advanced nanometer challenges under one design environment. The software platform (internal code name MAGIC II), will address a wide variety of IC design aspects among these are functional verification, geometric design-rules correctness, power management, reliability and design for manufacturing (DFM). The platform is targeted to support analog, digital and mixed signal designs, enabling efficient scalability and process migration. GBT's ML technology plans to be implemented to ensure fast performance; especially, with today's very large ICs in the domains of AI, IoT and data processing.

The most widely used description level in integrated circuit design is the artwork or layout level. This level describes integrated circuits in terms of "colored rectangles" (representing material on a chip) that can be composed to build up large designs. Associated with the colored rectangle terms of the layout level is a set of composition rules, called layout design rules. The layout composition rules provide a simple shallow model of composition that is based on a deep model of electrical properties and fabrication tolerances. If designers follow these rules, their designs are guaranteed to have adequate physical spacing on a chip [3, 4].