This study proposes a modularized deep learning-based loading protocol for optimal parameter estimation of Bouc-Wen (BW) class models. The protocol consists of two key components: optimal loading history construction and CNN-based rapid parameter estimation. Each component is decomposed into independent sub-modules tailored to distinct hysteretic behaviors-basic hysteresis, structural degradation, and pinching effect-making the protocol adaptable to diverse hysteresis models. Three independent CNN architectures are developed to capture the path-dependent nature of these hysteretic behaviors. By training these CNN architectures on diverse loading histories, minimal loading sequences, termed \textit{loading history modules}, are identified and then combined to construct an optimal loading history. The three CNN models, trained on the respective loading history modules, serve as rapid parameter estimators. Numerical evaluation of the protocol, including nonlinear time history analysis of a 3-story steel moment frame and fragility curve construction for a 3-story reinforced concrete frame, demonstrates that the proposed protocol significantly reduces total analysis time while maintaining or improving estimation accuracy. The proposed protocol can be extended to other hysteresis models, suggesting a systematic approach for identifying general hysteresis models.

Fig 1.1 Memory and non-memory components relationship Fig 1.2 Concept of artificial neural system in neuromorphic devices Fig 2.1 Memristor Symbol Fig 2.2 Current-voltage pinched hysteresis curve of memristor Fig 2.3 Memcapacitor Symbol Fig 2.4 Charge-voltage pinched hysteresis curve of memcapacitor Fig 2.5 Meminductor Symbol Fig 2.6 Current-flux pinched hysteresis curve of meminductor Fig 3.1 Device structure (a) TiOx-based memristor device (b) Si-based memcapacitor device Fig 3.2 Distribution of the TiOx memristor conductance in the HRS and LRS Fig 3.3 Training accuracy comparison of non-idealities (a) different device-todevice memductance variation (b) different cycle-to-cycle variation. Fig 3.4 The accuracy is influenced by the line resistance and the sneak paths Fig 3.5 Transistor level used in the framework (a) current sense amplifier (CSA), (b) voltage sense amplifier (VSA), (c) level shifter, and (d) successive approximation register (SAR) ADC. Fig 4.1 OTA (a) Symbol representation, and (b) MOSFETs realization Fig 4.2 Proposed meminductor emulator circuit Fig 4.3 An RLC neuromorphic circuit using meminductor for amoeba behavior Fig 4.4 Neuromorphic circuit using a meminductor for amoeba behavior Fig 4.5 Photograph of experimental setup Fig 4.6 Schematic of the hardware-implemented convolution layer Fig 4.7 Flowchart of CNN model training Fig 4.8 Structure of CNN implemented in software for classification of MNIST dataset Fig 4.9 Proposed meminductor based (a) VMM accelerator.

This device exhibits rich nonlinear properties and it is distinguished by a pinched hysteresis curve in the current-voltage (I/V) plane, which can be described by Kubo's response theory [3]. Since the experimental implementation of a memristor in a doped semiconductor by HP Labs in 2008 [4], memristors have garnered significant interest in several areas, including analog computing [5] and neuromorphic computing [6]. A notable application of memristors is the design of devices that mimic biological neural synapses [7] and neural networks [8]. Furthermore, memristor-enabled neuromorphic computing goes beyond the traditional von Neumann computing paradigm, avoiding the von Neumann bottleneck, which is one of the fundamental limitations of current classical computers [9, 10, 11]. Quantum computing [12] aims to revolutionize computation by exploiting exclusively quantum phenomena to surpass the capabilities of classical computers, as we can see from recent breakthroughs [13, 14, 15, 16, 17].