digital boltzmann vlsi
Digital Boltzmann VLSI for constraint satisfaction and learning
We built a high-speed, digital mean-field Boltzmann chip and SBus board for general problems in constraint satjsfaction and learning. Each chip has 32 neural processors and 4 weight update processors, supporting an arbitrary topology of up to 160 functional neurons. On-chip learning is at a theoretical maximum rate of 3.5 x 108 con(cid:173) nection updates/sec; recall is 12000 patterns/sec for typical condi(cid:173) tions. The chip's high speed is due to parallel computation of inner products, limited (but adequate) precision for weights and activa(cid:173) tions (5 bits), fast clock (125 MHz), and several design insights.
Digital Boltzmann VLSI for constraint satisfaction and learning
Murray, Michael, Leung, Ming-Tak, Boonyanit, Kan, Kritayakirana, Kong, Burg, James B., Wolff, Gregory J., Watanabe, Tokahiro, Schwartz, Edward, Stork, David G., Peterson, Allen M.
We built a high-speed, digital mean-field Boltzmann chip and SBus board for general problems in constraint satjsfaction and learning. Each chip has 32 neural processors and 4 weight update processors, supporting an arbitrary topology of up to 160 functional neurons. On-chip learning is at a theoretical maximum rate of 3.5 x 10
Digital Boltzmann VLSI for constraint satisfaction and learning
Murray, Michael, Leung, Ming-Tak, Boonyanit, Kan, Kritayakirana, Kong, Burg, James B., Wolff, Gregory J., Watanabe, Tokahiro, Schwartz, Edward, Stork, David G., Peterson, Allen M.
We built a high-speed, digital mean-field Boltzmann chip and SBus board for general problems in constraint satjsfaction and learning. Each chip has 32 neural processors and 4 weight update processors, supporting an arbitrary topology of up to 160 functional neurons. On-chip learning is at a theoretical maximum rate of 3.5 x 10
Digital Boltzmann VLSI for constraint satisfaction and learning
Murray, Michael, Leung, Ming-Tak, Boonyanit, Kan, Kritayakirana, Kong, Burg, James B., Wolff, Gregory J., Watanabe, Tokahiro, Schwartz, Edward, Stork, David G., Peterson, Allen M.
We built a high-speed, digital mean-field Boltzmann chip and SBus board for general problems in constraint satjsfaction and learning. Each chip has 32 neural processors and 4 weight update processors, supporting an arbitrary topology of up to 160 functional neurons. On-chip learning is at a theoretical maximum rate of 3.5 x 108 connection updates/sec;recall is 12000 patterns/sec for typical conditions. The chip's high speed is due to parallel computation of inner products, limited (but adequate) precision for weights and activations (5bits), fast clock (125 MHz), and several design insights.