Digital Boltzmann VLSI for constraint satisfaction and learning

Murray, Michael, Leung, Ming-Tak, Boonyanit, Kan, Kritayakirana, Kong, Burg, James B., Wolff, Gregory J., Watanabe, Tokahiro, Schwartz, Edward, Stork, David G., Peterson, Allen M.

–Neural Information Processing Systems 

We built a high-speed, digital mean-field Boltzmann chip and SBus board for general problems in constraint satjsfaction and learning. Each chip has 32 neural processors and 4 weight update processors, supporting an arbitrary topology of up to 160 functional neurons. On-chip learning is at a theoretical maximum rate of 3.5 x 10

Neural Information Processing Systems

Dec-31-1994

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Digital Boltzmann VLSI for constraint satisfaction and learning
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