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Event-Driven Digital-Time-Domain Inference Architectures for Tsetlin Machines
Lan, Tian, Shafik, Rishad, Yakovlev, Alex
Implementation Throughput GOp/s Energy Efficiency TOp/J Multi-class, synchronous 380 948.61 Multi-class, asynchronous BD 510 1381.65 Multi-class, proposed 402 3290.00 CoTM, synchronous 230 304.65 CoTM, asynchronous BD 350 397.60 CoTM, proposed 419 750.79 Under identical functionality, the proposed architecture delivers substantial energy efficiency while sustaining or enhancing inference throughput. For multi-class TM, energy efficiency rises by 247% over the synchronous digital baseline, with a throughput increase of 5.8%. Compared to the asynchronous BD architecture, the proposed design sacrifices a 21% throughput, improving energy efficiency by 138%. In CoTM, the architecture simultaneously boosts throughput by 82% and energy efficiency by 146% versus the synchronous reference. Compared to the asynchronous BD counterpart, this approach improves 20% throughput and 89% energy efficiency. Therefore, across both TM variants, this approach almost matches or exceeds the digital alternatives all around. C. Stat-of-the-art W ork Comparison Table III compares the proposed designs with several state-of-the-art ML accelerators.
- North America > United States (0.04)
- Europe > United Kingdom > England > Tyne and Wear > Newcastle (0.04)
Uncertainty Quantification in the Tsetlin Machine
Helin, Runar, Granmo, Ole-Christoffer, Shende, Mayur Kishor, Jiao, Lei, Zadorozhny, Vladimir I., Dumbre, Kunal Ganesh, Shafik, Rishad, Yakovlev, Alex
Data modeling using Tsetlin machines (TMs) is all about building logical rules from the data features. The decisions of the model are based on a combination of these logical rules. Hence, the model is fully transparent and it is possible to get explanations of its predictions. In this paper, we present a probability score for TM predictions and develop new techniques for uncertainty quantification to increase the explainability further. The probability score is an inherent property of any TM variant and is derived through an analysis of the TM learning dynamics. Simulated data is used to show a clear connection between the learned TM probability scores and the underlying probabilities of the data. A visualization of the probability scores also reveals that the TM is less confident in its predictions outside the training data domain, which contrasts the typical extrapolation phenomenon found in Artificial Neural Networks. The paper concludes with an application of the uncertainty quantification techniques on an image classification task using the CIFAR-10 dataset, where they provide new insights and suggest possible improvements to current TM image classification models.
- Europe > Norway (0.05)
- Europe > United Kingdom > England > Tyne and Wear > Newcastle (0.04)
- North America > United States (0.04)
Dynamic Tsetlin Machine Accelerators for On-Chip Training at the Edge using FPGAs
Mao, Gang, Rahman, Tousif, Maheshwari, Sidharth, Pattison, Bob, Shao, Zhuang, Shafik, Rishad, Yakovlev, Alex
--The increased demand for data privacy and security in machine learning (ML) applications has put impetus on effective edge training on Internet-of-Things (IoT) nodes. Edge training aims to leverage speed, energy efficiency and adaptability within the resource constraints of the nodes. This paper presents a Dynamic Tsetlin Machine (DTM) training accelerator as an alternative to DNN implementations. Underpinned on the V anilla and Coalesced Tsetlin Machine algorithms, the dynamic aspect of the accelerator design allows for a run-time reconfiguration targeting different datasets, model architectures, and model sizes without resynthesis. This makes the DTM suitable for targeting multivariate sensor-based edge tasks. Compared to DNNs, DTM trains with fewer multiply-accumulates, devoid of derivative computation. It is a data-centric ML algorithm that learns by aligning Tsetlin automata with input data to form logical propositions enabling efficient Lookup-T able (LUT) mapping and frugal Block RAM usage in FPGA training implementations. The proposed accelerator offers 2.54x more Giga operations per second per Watt (GOP/s per W) and uses 6x less power than the next-best comparable design. Index T erms --Edge Training, Coalesced Tsetlin Machines, Dynamic Tsetlin Machines, Embedded FPGA, Machine Learning Accelerator, On-Chip Learning, Logic-based-learning. ACHINE Learning (ML) offers a generalized approach to developing autonomous applications from "Internet-of-Things" (IoT) sensor data. Having ML execution units in close proximity to the sensor, at the so-called edge, enables faster task execution with high data security and privacy. However, sensor degradation and environmental factors may require recalibration [1] or user-personalized on-field training [2] to ensure continued functionality. Implementing solutions to these challenges is nontrivial. It requires finding the right balance between achieving the appropriate learning efficacy for the ML problem and the restrictive compute/ memory resources available on the platforms [3]. This work was supported by EPSRC EP/X036006/1 Scalability Oriented Novel Network of Event Triggered Systems (SONNETS) project and by EPSRC EP/X039943/1 UKRI-RCN: Exploiting the dynamics of self-timed machine learning hardware (ESTEEM) project. For ML inference tasks on edge nodes, these challenges have been widely explored, e.g., quantization [4], sparsity-based compression, and pruning for the most commonly used Deep Neural Network (DNN) models [3], [5], [6].
- Europe > United Kingdom > England > Tyne and Wear > Newcastle (0.04)
- North America > United States (0.04)
- Europe > Russia (0.04)
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- Research Report (0.64)
- Personal (0.46)
Pre-Sorted Tsetlin Machine (The Genetic K-Medoid Method)
Abstract--This paper proposes a machine learning pre-sort stage to traditional supervised learning using Tsetlin Machines. Initially, K data-points are identified from the dataset using an expedited genetic algorithm to solve the maximum dispersion problem. These are then used as the initial placement to run the K-Medoid clustering algorithm. Finally, an expedited genetic algorithm is used to align K independent Tsetlin Machines by maximising hamming distance. For MNIST level classification problems, results demonstrate up to 10% improvement in accuracy, 383X reduction in training time and 99X reduction in inference time.
- Asia > Middle East > Jordan (0.05)
- Europe > United Kingdom (0.04)
- Asia > Philippines (0.04)
TMComposites: Plug-and-Play Collaboration Between Specialized Tsetlin Machines
Tsetlin Machines (TMs) provide a fundamental shift from arithmetic-based to logic-based machine learning. Supporting convolution, they deal successfully with image classification datasets like MNIST, Fashion-MNIST, and CIFAR-2. However, the TM struggles with getting state-of-the-art performance on CIFAR-10 and CIFAR-100, representing more complex tasks. This paper introduces plug-and-play collaboration between specialized TMs, referred to as TM Composites. The collaboration relies on a TM's ability to specialize during learning and to assess its competence during inference. When teaming up, the most confident TMs make the decisions, relieving the uncertain ones. In this manner, a TM Composite becomes more competent than its members, benefiting from their specializations. The collaboration is plug-and-play in that members can be combined in any way, at any time, without fine-tuning. We implement three TM specializations in our empirical evaluation: Histogram of Gradients, Adaptive Gaussian Thresholding, and Color Thermometers. The resulting TM Composite increases accuracy on Fashion-MNIST by two percentage points, CIFAR-10 by twelve points, and CIFAR-100 by nine points, yielding new state-of-the-art results for TMs. Overall, we envision that TM Composites will enable an ultra-low energy and transparent alternative to state-of-the-art deep learning on more tasks and datasets.
- North America > United States > New York > New York County > New York City (0.04)
- North America > Canada > British Columbia > Metro Vancouver Regional District > Vancouver (0.04)
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