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Collaborating Authors

 Mackie, Stuart


Microelectronic Implementations of Connectionist Neural Networks

Neural Information Processing Systems

Three chip designs are described: a hybrid digital/analog programmable connection matrix, an analog connection matrix with adjustable connection strengths, and a digital pipelined best-match chip. The common feature of the designs is the distribution of arithmetic processing power amongst the data storage to minimize data movement.


Microelectronic Implementations of Connectionist Neural Networks

Neural Information Processing Systems

It is clear that conventional computers lag far behind organic computers when it comes to dealing with very large data rates in problems such as computer vision and speech recognition.