Google unwraps its gateway drug: Edge TPU chips for IoT AI code

Google has designed a low-power version of its homegrown AI math accelerator, dubbed it the Edge TPU, and promised to ship it to developers by October. Announced at Google Next 2018 today, the ASIC is a cutdown edition of its Tensor Processing Unit (TPU) family of in-house-designed coprocessors. TPUs are used internally at Google to power its machine-learning-based services, or are rentable via its public cloud. These chips are specific designed for and used to train neural networks and perform inference. Now the web giant has developed a cut-down inference-only version suitable for running in Internet-of-Things gateways.