Memory For Advanced Designs

The 2020 Designcon conference included many talks and exhibits with a storage and memory focus. Both Rambus and Teledyne LeCroy had tutorials on design and connectivity for leading edge electronic components and systems as well as testing memory systems. This piece will look at some material from the tutorials and exhibits that can inform us about disaggregated processing developments, high speed chip to chip interfaces and memory for AI applications. Rambus said that there are multiple drivers to disaggregate semiconductor die, often called die disaggregation or chiplets. Creating specialized chips used with other chips in a package allows the introduction of specialized technologies (such as co-packaged optical systems) as well as better cooling solutions and greater in-package memory.