Supplementary Material for Learning Semantic Representations to Verify Hardware Designs V asudevan, Jiang, Bieber, Singh, Shajaei, Ho, Sutton, NeurIPS 2021 Appendix A Additional figures

We show an example of RTL CDFG execution (simulation) over multiple cycles in Figure 4. The input stimulus and the branches covered by the simulation are shown in Figure 5.Figure 4: Input stimulus and corresponding branches that are covered. It can potentially be used to generate constraints. Figure 6 shows the context of our solution within the industrial verification flow. Design2V ec solution inbuilt into the constrained random verification environment.