Reconfigurable Neural Net Chip with 32K Connections
Graf, H. P., Janow, R., Henderson, D., Lee, R.
–Neural Information Processing Systems
We describe a CMOS neural net chip with a reconfigurable network architecture. It contains 32,768 binary, programmable connections arranged in 256 'building block' neurons. Several'building blocks' can be connected to form long neurons with up to 1024 binary connections or to form neurons with analog connections. Single-or multi-layer networks can be implemented with this chip. We have integrated this chip into a board system together with a digital signal processor and fast memory.
Neural Information Processing Systems
Dec-31-1991
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