A Appendix

Macros are relatively large, including DRAMs, caches, and IO interfaces. Pins are input/output interfaces for modules and are connected by wires directly, which have A net contains a set of pins connected by the same wires. Pins from the same net can form a net bounding box as Fig.8 It is the sum of half perimeter of net bounding boxes as Fig.8 (a)(b), where We give a set of placement results to explain the metrics in Fig.8. The density of Fig.8 (c) is 2.0 because g Relationship between pin offset and HPWL. The pin offset can affect the HPWL.