If it wasn't bad enough that Moore's Law improvements in the density and cost of transistors is slowing. At the same time, the cost of designing chips and of the factories that are used to etch them is also on the rise. Any savings on any of these fronts will be most welcome to keep IT innovation leaping ahead. One of the promising frontiers of research right now in chip design is using machine learning techniques to actually help with some of the tasks in the design process. We will be discussing this at our upcoming The Next AI Platform event in San Jose on March 10 with Elias Fallon, engineering director at Cadence Design Systems.

The creation of advanced electronic devices has become simultaneously more easy and difficult; there are more and more solutions out there, enough to address almost every application. The biggest problems we face include technology integration and cost-effective commercialization. This has given rise to the creation of integrated, scalable, device solutions, where a modular, building-block approach is available using stackable functionalities in a single application solution. This scalable approach is often supported by advanced software suites that streamline and simplify the design effort. One such solution set was recently announced by Lattice Semiconductor in their new low power FPGA platform, Lattice Nexus.