--Speculative execution attacks such as Spectre can be used to bypass the security isolation and steal information from other programs. Exploring speculative execution attacks on existing processors requires intensive manual reverse engineering and intimate knowledge of the processor . This reverse engineering-based approach requires extensive human effort, which is slow and not scalable. In this paper, we introduce SpecRL, a framework that utilizes reinforcement learning to explore speculative execution leaks in commercial-of-the shelf microprocessors. This reinforcement learning agent approach requires less reverse engineering effort while still be able to identify speculative execution vulnerabilties.

The primary objective of simultaneous machine translation (SiMT) is to minimize latency while preserving the quality of the final translation. Drawing inspiration from CPU branch prediction techniques, we propose incorporating branch prediction techniques in SiMT tasks to reduce translation latency. Specifically, we utilize a language model as a branch predictor to predict potential branch directions, namely, future source words. Subsequently, we utilize the predicted source words to decode the output in advance. When the actual source word deviates from the predicted source word, we use the real source word to decode the output again, replacing the predicted output. To further reduce computational costs, we share the parameters of the encoder and the branch predictor, and utilize a pre-trained language model for initialization. Our proposed method can be seamlessly integrated with any SiMT model. Extensive experimental results demonstrate that our approach can improve translation quality and latency at the same time. Our code is available at https://github.com/YinAoXiong/simt_branch_predictor .

Branch prediction is an architectural feature that speeds up the execution of branch instruction on pipeline processors and reduces the cost of branching. Recent advancements of Deep Learning (DL) in the post Moore's Law era is accelerating areas of automated chip design, low-power computer architectures, and much more. Traditional computer architecture design and algorithms could benefit from dynamic predictors based on deep learning algorithms which learns from experience by optimizing its parameters on large number of data. In this survey paper, we focus on traditional branch prediction algorithms, analyzes its limitations, and presents a literature survey of how deep learning techniques can be applied to create dynamic branch predictors capable of predicting conditional branch instructions. Prior surveys in this field focus on dynamic branch prediction techniques based on neural network perceptrons. We plan to improve the survey based on latest research in DL and advanced Machine Learning (ML) based branch predictors.

Recent years have seen stagnating improvements to branch predictor (BP) efficacy and a dearth of fresh ideas in branch predictor design, calling for fresh thinking in this area. This paper argues that looking at BP from the viewpoint of Reinforcement Learning (RL) facilitates systematic reasoning about, and exploration of, BP designs. We describe how to apply the RL formulation to branch predictors, show that existing predictors can be succinctly expressed in this formulation, and study two RL-based variants of conventional BPs.

At the International Solid-State Circuits Conference held earlier this month, some solid information has come to surface on a subject near and dear to many enthusiast hearts right now: AMD's upcoming Ryzen CPU line. As far as credibility, the information comes in fairly convincing form. AMD's claims are backed with die shots of actual AMD Ryzen cores and further supported by more shots of their CCX (core complex) modules. From these shots, we can guess at several things, and further more see evidence for several of their claims.To get to the meat of the matter, let's start with a die shot of a single AMD Ryzen core.The main thing to notice here is of course the fact that each core has only one integer and FPU section, rather than splitting an FPU between two integer units. This represents a major design departure from earlier designs by AMD such as Bulldozer, Piledriver, etc, but is not entirely a surprise as Ryzen has been known (or at the very least, strongly suspected) to utilize such a config for quite some time now.