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bit-serial in-cache acceleration

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Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks – Arxiv Vanity

#artificialintelligenceMay-11-2018, 11:00:16 GMT

We use the addition of two vectors of 4-bit numbers to explain how addition works in the SRAM. The 2 words that are going to be added together have to be put in the same bit line. The vectors A and B should be aligned in the array like Figure 5. Vector A occupies the first 4 rows of the SRAM array and vector B the next 4 rows. Another 4 empty rows of storage are reserved for the results. There is a row of latches inside the column peripheral for the carry storage.

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Technology: Information Technology > Artificial Intelligence > Machine Learning > Neural Networks > Deep Learning (0.40)

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