Conductance can vary based on everything from the manufacturing of the chip to environmental factors. The variation can add up and throw neural networks off. Early approaches used analog and digital together, with digital-to-analog and analog-to-digital convertors between layers. However, this needs to be limited, as conversion is slower and more energy-intensive than staying analog. It can create its own bottleneck.

Rain Neuromorphics has taped out a demonstration chip for its brain-inspired analog architecture that employs a 3D array of randomly-connected memristors to compute neural network training and inference at extremely low power. Switching to entirely analog hardware for AI computation could allow a massive reduction in the power consumed by AI workloads. While some commercial chips currently use analog processor-in-memory techniques, they require digital conversion between network layers, consuming significant power. The limitations of current analog devices also means they can't be used for training AI models since they are incompatible with back-propagation, the algorithm widely used for AI training. Rain's aim is to build a complete analog chip, solving these issues with a combination of new hardware and a new training algorithm.

We introduce the IBM Analog Hardware Acceleration Kit, a new and first of a kind open source toolkit to simulate analog crossbar arrays in a convenient fashion from within PyTorch (freely available at https://github.com/IBM/aihwkit). The toolkit is under active development and is centered around the concept of an "analog tile" which captures the computations performed on a crossbar array. Analog tiles are building blocks that can be used to extend existing network modules with analog components and compose arbitrary artificial neural networks (ANNs) using the flexibility of the PyTorch framework. Analog tiles can be conveniently configured to emulate a plethora of different analog hardware characteristics and their non-idealities, such as device-to-device and cycle-to-cycle variations, resistive device response curves, and weight and output noise. Additionally, the toolkit makes it possible to design custom unit cell configurations and to use advanced analog optimization algorithms such as Tiki-Taka. Moreover, the backward and update behavior can be set to "ideal" to enable hardware-aware training features for chips that target inference acceleration only. To evaluate the inference accuracy of such chips over time, we provide statistical programming noise and drift models calibrated on phase-change memory hardware. Our new toolkit is fully GPU accelerated and can be used to conveniently estimate the impact of material properties and non-idealities of future analog technology on the accuracy for arbitrary ANNs.