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Satyanarayana, Srinagesh
A Reconfigurable Analog VLSI Neural Network Chip
Satyanarayana, Srinagesh, Tsividis, Yannis P., Graf, Hans Peter
The distributed-neuron synapses are arranged in blocks of 16, which we call '4 x 4 tiles'. Switch matrices are interleaved between each of these tiles to provide programmability of interconnections. With a small area overhead (15 %), the 1024 units of the network can be rearranged in various configurations. Some of the possible configurations are, a 12-32-12 network, a 16-12-12-16 network, two 12-32 networks etc. (the numbers separated by dashes indicate the number of units per layer, including the input layer). Weights are stored in analog form on MaS capacitors.
A Reconfigurable Analog VLSI Neural Network Chip
Satyanarayana, Srinagesh, Tsividis, Yannis P., Graf, Hans Peter
The distributed-neuron synapses are arranged inblocks of 16, which we call '4 x 4 tiles'. Switch matrices are interleaved between each of these tiles to provide programmability ofinterconnections. With a small area overhead (15 %), the 1024 units of the network can be rearranged in various configurations. Someof the possible configurations are, a 12-32-12 network, a 16-12-12-16 network, two 12-32 networks etc. (the numbers separated bydashes indicate the number of units per layer, including the input layer). Weights are stored in analog form on MaS capacitors.
A Reconfigurable Analog VLSI Neural Network Chip
Satyanarayana, Srinagesh, Tsividis, Yannis P., Graf, Hans Peter
The distributed-neuron synapses are arranged in blocks of 16, which we call '4 x 4 tiles'. Switch matrices are interleaved between each of these tiles to provide programmability of interconnections. With a small area overhead (15 %), the 1024 units of the network can be rearranged in various configurations. Some of the possible configurations are, a 12-32-12 network, a 16-12-12-16 network, two 12-32 networks etc. (the numbers separated by dashes indicate the number of units per layer, including the input layer). Weights are stored in analog form on MaS capacitors.
Stochastic Learning Networks and their Electronic Implementation
Alspector, Joshua, Allen, Robert B., Hu, Victor, Satyanarayana, Srinagesh
This paper focuses on the issue of learning in these networks especially with regard to their implementation in an electronic system. Learning phenomena that have been studied include associative memoryllJ.
Stochastic Learning Networks and their Electronic Implementation
Alspector, Joshua, Allen, Robert B., Hu, Victor, Satyanarayana, Srinagesh
This paper focuses on the issue of learning in these networks especially with regard to their implementation in an electronic system. Learning phenomena that have been studied include associative memoryllJ.