Constrained deep neural network architecture search for IoT devices accounting for hardware calibration
Scheidegger, Florian, Benini, Luca, Bekas, Costas, Malossi, A. Cristiano I.
–Neural Information Processing Systems
Deep neural networks achieve outstanding results for challenging image classification tasks. However, the design of network topologies is a complex task, and the research community is conducting ongoing efforts to discover top-accuracy topologies, either manually or by employing expensive architecture searches. We propose a unique narrow-space architecture search that focuses on delivering low-cost and rapidly executing networks that respect strict memory and time requirements typical of Internet-of-Things (IoT) near-sensor computing platforms. Our approach provides solutions with classification latencies below 10 ms running on a low-cost device with 1 GB RAM and a peak performance of 5.6 GFLOPS. The narrow-space search of floating-point models improves the accuracy on CIFAR10 of an established IoT model from 70.64% to 74.87% within the same memory constraints.
Neural Information Processing Systems
Mar-18-2020, 23:01:27 GMT
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