Hiroo Ota (center left), CEO of Kioxia Holdings, and others unveil Kioxia's new 3D flash memory chip at its Kitakami plant in Kitakami, Iwate Prefecture, on Friday. Kioxia Holdings has started shipping samples of its next-generation flash memory chips to artificial-intelligence data center operators, seeking to gain ground in the lucrative business against rivals. The Tokyo-based chipmaker's latest high-density 3D flash memory chips aim to better meet AI data center needs with better efficiency and transmission speeds. The 332-layer 10th-generation chips pack more data into silicon and can store 59% more data compared with its previous flagship 8th-generation chip, the company said Friday. Production will take place at the company's second manufacturing facility at its Kitakami plant in Iwate Prefecture, which began operating in September last year.

PCWorld reports that Valve's Steam Machine ships with a single 16GB DDR5-5600 SODIMM, leaving one memory slot empty and causing a 10% performance loss compared to dual-channel configurations. Users can upgrade to 32GB by adding another 16GB SODIMM for around $200, but the process requires complex disassembly as demonstrated in teardowns. The Steam Machine's high price combined with its single-stick RAM limitation makes it a questionable value proposition for gamers seeking optimal performance. Valve will sell you a Steam Machine starting today, at least if you signed up earlier this week and you have a little bit of luck. Early supplies are expected to be extremely limited, as Valve is dealing with the same hardware issues as the entire industry. It comes with just 16GB of RAM, which is a little light for a gaming desktop. But there's something you should know about it that isn't on the spec list. The Steam Machine is using semi-standard parts, at least for RAM and storage, including familiar SODIMM sticks that go into laptops.

Microsoft's budget Surface returns with 8GB RAM configurations, which PCWorld notes can cause performance issues when running multiple applications and browser tabs on Windows devices. Microsoft justifies 8GB as sufficient for basic productivity tasks and is working to optimize Windows' memory footprint, including reducing usage for features like Widgets. Apple's integrated hardware-software approach provides superior efficiency advantages over Windows devices in similar budget scenarios, offering better performance even under demanding conditions. After shipping the Surface Laptop and Pro for business customers starting at about $2,000, Microsoft has come down to earth. Microsoft is releasing a smaller Surface Laptop and Pro for under $1,000, but with a callback to the bad old days of 8GB of system memory.

Open-source foundation models have seen rapid adoption and development, enabling powerful general-purpose capabilities across diverse domains. However, fine-tuning large foundation models for domain-specific or personalized tasks remains prohibitively expensive for most users due to the significant memory overhead beyond that of inference. We introduce EMLoC, an Emulator-based Memory-efficient fine-tuning framework with LoRACorrection, which enables model fine-tuning within the same memory budget required for inference. EMLoC constructs a task-specific light-weight emulator using activation-aware singular value decomposition (SVD) on a small downstream calibration set. Fine-tuning then is performed on this lightweight emulator via LoRA. To tackle the misalignment between the original model and the compressed emulator, we propose a novel compensation algorithm to correct the fine-tuned LoRA module, which thus can be merged into the original model for inference. EMLoC supports flexible compression ratios and standard training pipelines, making it adaptable to a wide range of applications. Extensive experiments demonstrate that EMLoC outperforms other baselines across multiple datasets and modalities. Moreover, without quantization, EMLoC enables fine-tuning of a 38B model, which originally required 95GB of memory, on a single 24GB consumer GPU--bringing efficient and practical model adaptation to individual users.

As the economic and environmental costs of training and deploying large vision or language models increase dramatically, analog in-memory computing (AIMC) emerges as a promising energy-efficient solution. However, the training perspective, especially its training dynamics, is underexplored. In AIMC hardware, the trainable weights are represented by the conductance of resistive elements and updated using consecutive electrical pulses. While the conductance changes by a constant in response to each pulse, in reality, the change is scaled by asymmetric and non-linear response functions, leading to a non-ideal training dynamics. This paper provides a theoretical foundation for gradient-based training on AIMC hardware with nonideal response functions.

Reasoning models have demonstrated impressive performance in self-reflection and chain-of-thought reasoning. However, they often produce excessively long outputs, leading to prohibitively large key-value (KV) caches during inference. While chain-of-thought inference significantly improves performance on complex reasoning tasks, it can also lead to reasoning failures when deployed with existing KV cache compression approaches. To address this, we propose Redundancyaware KVCache Compression for Reasoning models (R-KV), a novel method specifically targeting redundant tokens in reasoning models. Our method preserves nearly 100% of the full KV cache performance using only 10% of the KV cache, substantially outperforming existing KV cache baselines, which reaches only 60% of the performance. Remarkably, R-KV even achieves 105% of full KV cache performance with 16% of the KV cache. This KV-cache reduction also leads to a 90% memory saving and a 6.6 throughput over standard chain-ofthought reasoning inference. Experimental results show that R-KV consistently outperforms existing KV cache compression baselines across two mathematical reasoning datasets.

Gaussian processes are a powerful tool for modeling continuous fields, but their naive $\mathcal{O}(N^3)$ computational cost and $\mathcal{O}(N^2)$ memory requirement often limit their practical use. Vecchia's approximation is a sparse precision matrix approximation for stationary, decaying kernels that conditions each point only on its $k$ nearest neighbors. We present GraphGP, a GPU algorithm for Vecchia's approximation that scales to nearly a billion parameters with linear time and memory requirements, handling arbitrary point distributions over a large dynamic range. Our key contributions are (1) a bit-reversed k-d tree ordering that allows efficient neighbor searches while also maximizing batch parallelism, and (2) a differentiable CUDA implementation, which is substantially faster and more memory efficient than our pure JAX baseline. GraphGP provides the building blocks for inference, including forward generation, inverse application, log-determinant, and kernel parameter derivatives.

Recently, several works have shown that natural modifications of the classical conditional gradient method (aka Frank-Wolfe algorithm) for constrained convex optimization, provably converge with a linear rate when the feasible set is a polytope, and the objective is smooth and strongly-convex. However, all of these results suffer from two significant shortcomings: i) large memory requirement due to the need to store an explicit convex decomposition of the current iterate, and as a consequence, large running-time overhead per iteration ii) the worst case convergence rate depends unfavorably on the dimension In this work we present a new conditional gradient variant and a corresponding analysis that improves on both of the above shortcomings. In particular, both memory and computation overheads are only linear in the dimension, and in addition, in case the optimal solution is sparse, the new convergence rate replaces a factor which is at least linear in the dimension in previous works, with a linear dependence on the number of non-zeros in the optimal solution At the heart of our method, and corresponding analysis, is a novel way to compute decomposition-invariant away-steps. While our theoretical guarantees do not apply to any polytope, they apply to several important structured polytopes that capture central concepts such as paths in graphs, perfect matchings in bipartite graphs, marginal distributions that arise in structured prediction tasks, and more. Our theoretical findings are complemented by empirical evidence that shows that our method delivers state-of-the-art performance.

The continued scaling of flash memory technology into smaller process nodes, combined with the increased information capacity of each flash cell (i.e, storing more bits per cell), has placed NAND flash memory at the forefront of modern storage technology.

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