Models of design processes provide guidance in the development of knowledge-based systems for design. The basis for such models comes from research in design theory and methodology as well as problem solving in AI. Three models are presented: decomposition, case-based reasoning, and transformation. Each model provides a formalism for representing design knowledge and experience in distinct and complementary forms.

This article discusses building a computable design process model, which is a prerequisite for realizing intelligent computer-aided design systems. First, we introduce general design theory, from which a descriptive model of design processes is derived. In this model, the concept of metamodels plays a crucial role in describing the evolutionary nature of design. Second, we show a cognitive design process model obtained by observing design processes using a protocol analysis method. We then discuss a computable model that can explain most parts of the cognitive model and also interpret the descriptive model. In the computable model, a design process is regarded as an iterative logical process realized by abduction, deduction, and circumscription. We implemented a design simulator that can trace design processes in which design specifications and design solutions are gradually revised as the design proceeds.

Contrary to many prevailing approaches to knowledge acquisition, Laps, our expert-interviewing software, begins by soliciting cases from the expert, but it does not end there. Its uniqueness lies in the fact that it interweaves knowledge gathering, organizing, and testing. Laps begins with a case in the form of a sample solution path elicited from the domain expert. This sample solution path is refined by a process called dechunking, which facilitates finding a model of the expert's reasoning process. The model guides the determination of the structure of alternatives tables at an effective level of abstraction. Once these tables have been set up, the expert is able to produce row after row on his own until a complete rule base is built. A rule generator currently produces rules in Clips or M.1 syntax.

It (McDermott 1988), and the idea of generic also helps to explicitly focus on how to go tasks and task-specific architectures (Chandrasekaran from the knowledge level to the symbol or 1983). These various proposals are program level. I call this in-between level the obviously related to each other, which makes knowledge-use level. At the knowledge-use it desirable to construct a synthesis that combines level, we focus on issues such as how the their strengths. Such a synthesis is presented overall task will be decomposed into manageable here in the form of a componential subtasks, what ordering will be imposed framework. The framework stresses modularity on the tasks, what kind of access to knowledge and consideration of the pragmatic constraints will be needed (and, consequently, what of the domain.

Jim when we want to define the class of should be justified by something Schmolze argued that if you think of people who work in specific institutions), other than the code implementing a sort of lingua franca for knowledge (2) when a concept definition the system. However, interpreting the representation, you can't be committed depends on the assertional properties two terms efficient and principled as to the difference between terminological of its instances (as with gray elephants, worst-case tractability and soundness and assertional knowledge for example), and (3) when and completeness with respect to the or even between roles and concepts.

We have fabricated a test chip in 2 micron CMOS technology that embodies these ideas and we report our evaluation of the microchip and our plans for improvements. Knowledge is encoded in the test chip by presenting digital patterns to it that are examples of a desired input-output Boolean mapping. This knowledge is learned and stored entirely on chip in a digitally controlled synapse-like element in the form of connection strengths between neuron-like elements. The only portion of this learning system which is off chip is the VLSI test equipment used to present the patterns. This learning system uses a modified Boltzmann machine algorithm[3] which, if simulated on a serial digital computer, takes enormous amounts of computer time. Our physical implementation is about 100,000 times faster. The test chip, if expanded to a board-level system of thousands of neurons, would be an appropriate architecture for solving artificial intelligence problems whose solutions are hard to specify using a conventional rule-based approach. Examples include speech and pattern recognition and encoding some types of expert knowledge.

We discuss in this paper architectures for executing probabilistic rule-bases in a parallel manner, using as a theoretical basis recently introduced information-theoretic models. We will begin by describing our (non-neural) learning algorithm and theory of quantitative rule modelling, followed by a discussion on the exact nature of two particular models. Finally we work through an example of our approach, going from database to rules to inference network, and compare the network's performance with the theoretical limits for specific problems.

We have fabricated a test chip in 2 micron CMOS technology that embodies these ideas and we report our evaluation of the microchip and our plans for improvements. Knowledge is encoded in the test chip by presenting digital patterns to it that are examples of a desired input-output Boolean mapping. This knowledge is learned and stored entirely on chip in a digitally controlled synapse-like element in the form of connection strengths between neuron-like elements. The only portion of this learning system which is off chip is the VLSI test equipment used to present the patterns. This learning system uses a modified Boltzmann machine algorithm[3] which, if simulated on a serial digital computer, takes enormous amounts of computer time. Our physical implementation is about 100,000 times faster. The test chip, if expanded to a board-level system of thousands of neurons, would be an appropriate architecture for solving artificial intelligence problems whose solutions are hard to specify using a conventional rule-based approach. Examples include speech and pattern recognition and encoding some types of expert knowledge.

We discuss in this paper architectures for executing probabilistic rule-bases in a parallel manner, using as a theoretical basis recently introduced information-theoretic models. We will begin by describing our (non-neural) learning algorithm and theory of quantitative rule modelling, followed by a discussion on the exact nature of two particular models. Finally we work through an example of our approach, going from database to rules to inference network, and compare the network's performance with the theoretical limits for specific problems.

We have fabricated a test chip in 2 micron CMOS technology that embodies these ideas and we report our evaluation of the microchip and our plans for improvements. Knowledge is encoded in the test chip by presenting digital patterns to it that are examples of a desired input-output Boolean mapping. This knowledge is learned and stored entirely on chip in a digitally controlled synapse-like element in the form of connection strengths between neuron-like elements. The only portion of this learning system which is off chip is the VLSI test equipment used to present the patterns. This learning system uses a modified Boltzmann machine algorithm[3] which, if simulated on a serial digital computer, takes enormous amounts of computer time. Our physical implementation is about 100,000 times faster. The test chip, if expanded to a board-level system of thousands of neurons, would be an appropriate architecture for solving artificial intelligence problems whose solutions are hard to specify using a conventional rule-based approach. Examples include speech and pattern recognition and encoding some types of expert knowledge.