On the heels of its dual announcement at the Open Compute Project Summit in Amsterdam this week (see related story), Xilinx yesterday disclosed that AMD and Xilinx have teamed to set an AI inference processing record of 30,000 images per second. The joint work of the two companies, announced at the Xilinx Developer Forum in San Jose by Xilinx CEO Victor Peng and AMD CTO Mark Papermaster, connects AMD's EPYC CPUs and the new Xilinx Alveo FPGA accelerator card, announced yesterday at the OCP Summit. The record, running a batch size of 1 and Int8 precision, was accomplished on a system that leverages two AMD EPYC 7551 server CPUs with PCIe connectivity, along with eight Alveo U250 accelerator cards. In a blog post, Xilinx said the inference performance is powered by Xilinx ML Suite, which allows developers to optimize and deploy accelerated inference and supports various machine learning frameworks, such as TensorFlow. The benchmark was performed on the GoogLeNet convolutional neural network.
Microsoft is set to capitalize on its work on integrating field programmable gate arrays (FPGAs) into servers for machine learning workloads, by launching a specialized Azure cloud service. Project Brainwave will be offered in preview, with a limited set of capabilities and allocations, and will only be available in the East US 2 region to begin with. The company also plans to offer Brainwave servers as on-premises edge deployments. "I think this is a first step in making the FPGAs more of a general-purpose platform for customers," Mark Russinovich, chief technical officer for Azure, said at Microsoft Build conference. Brainwave uses Intel's Stratix 10 FPGAs, and builds upon Microsoft's previous work with these chips.
At this week's Xilinx Developers Forum (XDF) in San Jose, California, Xilinx announced "Vitis" – a new framework for developing applications that use Xilinx programmable logic devices such as FPGAs, ACAPs, MPSoCs, RFSoCs, and all the other acronyms they can come up with that refer to what we'd call "FPGAs." With an abundance of grandiosity, the company proclaimed that Vitis was "five years and a total of 1,000 man-years in the making." We don't frequently encounter person-millenia metrics for new product announcements. Even if we assume that they started this in 1984 when Xilinx was founded, they would still have needed at least 28 engineers writing code full time for Vitis over that 35 year span. Spoiler: engineering-eons aside, Vitis IS impressive, and more importantly, is likely to mature to be even more impressive over the coming years.
AMD is acquiring chip designer Xilinx for $35 billion in stock to "significantly" expand the range of products it makes and customers it reaches, particularly in high performance computing. As the Wall Street Journal noted, Xilinx's easily customizable FPGA (field-programmable gate array) chips are used in a variety of places AMD wouldn't have even considered before, from 5G systems to the F-35 to self-driving cars. The newly-bought company also specializes in adaptive systems-on-chip, accelerators and smart networking devices found in data centers, edge computing and end devices. AMD expects the Xilinx deal to take a while to wrap up. It should close by the end of 2021, the company said.
Semiconductor company Xilinx is taking the wraps off of its software programmable chip design that it claims is part of an entirely new computing category. It's called the Adaptive Compute Acceleration Platform (ACAP), and Xilinx says it will make data center servers highly programmable with exponential increases to performance. The technology behind ACAP is highly technical for the average Joe, but here's how Xilinx frames the concept against existing chip designs. According to Xilinx, ACAP is different from field-programmable gate array (FPGA) fabric -- an integrated circuit that can be further configured after manufacturing -- as well as SoCs and GPUs, because "the designer no longer needs to utilize programmable logic to build the connectivity infrastructure, it is programmable using high level languages that provide flexibility and ease of use while at the same time delivering performance benefits and power efficiency an order of magnitude or more greater than a CPU. This enables a fundamentally different software centric design flow since all of the connectivity infrastructure is natively software programmable."