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RISC-V International Ratifies 15 New Specifications, Opening Up New Possibilities for RISC-V Designs - RISC-V International

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ZURICH – Dec. 2, 2021 – RISC-V International, a global open hardware standards organization, today announced that RISC-V members have ratified 15 new specifications – representing more than 40 extensions – for the free and open RISC-V instruction set architecture (ISA). Most notably, RISC-V members ratified the Vector, Scalar Cryptography, and Hypervisor specifications which will help unlock new opportunities for developers creating RISC-V applications for artificial intelligence (AI) and machine learning (ML), the Internet of Things (IoT), connected and autonomous cars, data centers, and beyond. "In 2021, RISC-V International made huge leaps in our technical progress as we ratified 15 specifications that are critical for the future of computing," said Krste Asanović, Chair of the RISC-V International Board of Directors. "The development of these specifications really showcased the incredible benefits of open collaboration across companies and geographies as members worked together to develop novel approaches for the latest computing requirements." The RISC-V Vector specification will help accelerate the computation of data intensive operations like ML inference for audio, vision, and voice processing.


Linux Foundation and RISC-V International launch free RISC-V training classes

ZDNet

RISC-V, the emerging open-source instruction set processor architecture, is growing up. Sure, most of the attention has come from hardware hackers playing on RISC-V processors on development boards from companies such as SiFive. But, according to RISC-V CTO Mark Himelstein, RISC-V processors have already found a home in data centers and Alibaba cloud servers. So, it's high time for classes on how to use this new open-source hardware architecture. Then you need to know Linux and open-source software.


GPU from Imagination works with RISC-V

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The activity around creating a legit graphics processor for RISC-V chip designs, an emerging competitor to x86 and ARM, is gaining steam. Special interest groups at RISC-V next year will expand the focus on extensions for shaders and advanced matrix operations, which is important for artificial intelligence and machine learning, Mark Himelstein, chief technology officer at RISC-V, told The Register. RISC-V International, which developed the instruction set architecture, has interest groups develop extensions that users can add to their chip designs. In 2021, 16 RISC-V extensions were ratified, Himelstein said, and that number will grow next year. Many new extensions were part of mainstream computing chips announced this year at the RISC-V Summit.


RISC-V Gains Its Footing

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The RISC-V instruction-set architecture, which started as a UC Berkeley project to improve energy efficiency, is gaining steam across the industry.


Rediscovering RISC-V: Apple M1 sparks renewed interest in non-x86 architectures

ZDNet

RISC-V is, like x86 and ARM, an instruction set architecture (ISA). Unlike x86 and ARM, it is a free and open standard that anyone can use without getting locked into someone else's processor designs or paying costly license fees. Apple's recent move to redesign its Mac computers around chips that it fabricates for itself, replacing Intel, has cast a new spotlight around a class of processor that there's a very good chance you own right now. RISC-V (pronounced RISC-5) is the brainchild of UC Berkeley professors David Patterson and Krste Asanović. Patterson has a talent for catchy acronyms and architectures as a developer of RISC (Reduced Instruction Set Computing) and RAID (Redundant Array of Inexpensive Disks) in the 1980s.