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RISC-V International Ratifies 15 New Specifications, Opening Up New Possibilities for RISC-V Designs - RISC-V International


ZURICH – Dec. 2, 2021 – RISC-V International, a global open hardware standards organization, today announced that RISC-V members have ratified 15 new specifications – representing more than 40 extensions – for the free and open RISC-V instruction set architecture (ISA). Most notably, RISC-V members ratified the Vector, Scalar Cryptography, and Hypervisor specifications which will help unlock new opportunities for developers creating RISC-V applications for artificial intelligence (AI) and machine learning (ML), the Internet of Things (IoT), connected and autonomous cars, data centers, and beyond. "In 2021, RISC-V International made huge leaps in our technical progress as we ratified 15 specifications that are critical for the future of computing," said Krste Asanović, Chair of the RISC-V International Board of Directors. "The development of these specifications really showcased the incredible benefits of open collaboration across companies and geographies as members worked together to develop novel approaches for the latest computing requirements." The RISC-V Vector specification will help accelerate the computation of data intensive operations like ML inference for audio, vision, and voice processing.

Open-source chip mimics Linux's path to take on closed x86 and ARM CPUs


If you're buying a PC or server, you've likely considered chips based on x86 or, perhaps less often, the ARM architecture. But like Linux in software, an open-source chip project is out to break the dominance of proprietary chips offered by Intel, AMD, and ARM. The RISC-V open-source architecture, created by researchers at the University of California, Berkeley, in 2010, is open to all who want to use it. The RISC-V design can be modified for PCs, servers, smartphones, wearables, and other devices. A startup called SiFive is the first to make a business out of the RISC-V architecture.

RISC-V Gains Its Footing


The RISC-V instruction-set architecture, which started as a UC Berkeley project to improve energy efficiency, is gaining steam across the industry.

Data61's seL4 security enforcement now available to the RISC-V ecosystem


The Commonwealth Scientific and Industrial Research Organisation's (CSIRO) Data61 has completed the proof of implementation correctness of the open-source seL4 microkernel for the RISC-V instruction-set architecture (ISA). Unlike most other ISA designs, the RISC-V ISA is provided under open source licences that do not require fees. According to Data61, many organisations are developing processors based on the open RISC-V ISA, targeting platforms ranging from embedded and cyberphysical systems to high-end servers. Data61's development means that seL4's security enforcement is now available to the RISC-V ecosystem. "We aim to shift the software industry away from ad-hoc, unreliable engineering practices, and towards principled approaches based on the fundamentals of mathematics," leader of the proof engineering team of Data61's Trustworthy Systems Research group Dr Rafal Kolanski said.

European Processor Initiative Tapes Out Their First RISC-V Test Chip


Recently, the EPI announced that it has developed its first HPC chip using RISC-V technology and is now in the stages of having the device fabricated. What is the EPI, what will the new device be capable of, and how does this release demonstrate the potential of RISC-V architecture? The European Processor Initiative collects different institutions across the EU that aim to develop and create high-performance, low-power chips for use in supercomputers and other big data applications. Currently, most processors used in supercomputers are proprietary and often sourced from foreign nations. For example, the main processor technology currently in use is x86/x64, and these processors are only designed and manufactured by two companies; Intel and AMD.